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LTC4253A-ADJ - 48V Hot Swap Controller with Sequencer
FEATURES

DESCRIPTIO
Allows Safe Board Insertion and Removal from a Live - 48V Backplane Floating Topology Permits Very High Voltage Operation Adjustable Analog Current Limit with Breaker Timer Fast Response Time Limits Peak Fault Current Adjustable Undervoltage/Overvoltage Protection with 1% Threshold Accuracy Three Sequenced Power Good Outputs Adjustable Soft-Start Current Limit Adjustable Timer with Drain Voltage Accelerated Response Latchoff After Fault Available in 20-Pin SSOP and 20-Pin (4mm x 4mm) QFN Packages
The LTC(R)4253A-ADJ negative voltage Hot SwapTM controller allows a board to be safely inserted and removed from a live backplane. Output current is controlled by three stages of current-limiting: a timed circuit breaker, active current limiting and a fast feedforward path that limits peak current under worst-case catastrophic fault conditions. The LTC4253A-ADJ latches off after a circuit fault. Undervoltage and overvoltage detectors with adjustable thresholds and hystereses disconnect the load whenever the input supply exceeds the desired operating range. The LTC4253A-ADJ's supply input is shunt-regulated, allowing safe operation with very high supply voltages. A multifunction timer delays initial start-up and controls the circuit breaker's response time. The circuit breaker's response time can be accelerated by sensing excessive MOSFET drain voltage. An adjustable soft-start circuit controls MOSFET inrush current at start-up. Three power good outputs can be sequenced to enable external power modules at start-up or disable them if the circuit breaker trips. The LTC4253A-ADJ is available in 20-pin SSOP and 20-pin (4mm x 4mm) QFN packages.
, LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patent pending.
APPLICATIO S

- 48V Distributed Power Systems Negative Power Supply Control Central Office Switching High Availability Servers Disk Arrays
TYPICAL APPLICATIO
- 48V RTN - 48V RTN 1F 255k 1% 10nF EN2 EN3 VIN LTC4253A-ADJ RESET UVL UV OVL 0.536k 1% 20k 1% - 48V A B3100* OV 33nF 0.1F 0.68F SS SQTIMER GATE TIMER SEL SENSE VEE PWRGD1 PWRGD2 PWRGD3 DRAIN
- 48V/2.5A Hot Swap Controller
2.5k 15k(1/4W)/6 5.6k
VIN 5.6k
+
100F 5.6k
LOAD1 LOAD2 EN EN EN LOAD3
1.24k 1% 2.1k 1%
4253A TA01
1M
IRF530S
MOC207
*DIODES, INC.
10 10nF 0.02
- 48V B
B3100*
U
Start-Up Behavior
GATE 10V SS 1V SENSE 50mV VOUT 50V 1ms/DIV
4253A TA01b
U
U
4253a-adjf
1
LTC4253A-ADJ
ABSOLUTE
AXI U RATI GS
Current into VIN (100s Pulse) ........................... 100mA Current into DRAIN (100s Pulse) ........................ 20mA VIN, DRAIN Minimum Voltage............................... - 0.3V Input/Output (Except SENSE and DRAIN) Voltage ...................................- 0.3V to 16V SENSE Voltage ..........................................- 0.6V to 16V Current Out of SENSE (20s Pulse) .................. - 200mA Maximum Junction Temperature .......................... 125C
PACKAGE/ORDER I FOR ATIO
TOP VIEW EN2 PWRGD2 PWRGD1 VIN RESET SS SEL SENSE VEE 1 2 3 4 5 6 7 8 9 20 PWRGD3 19 EN3 18 SQTIMER 17 TIMER 16 UVL 15 UV 14 OVL 13 OV 12 DRAIN 11 GATE
PWRGD1
PWRGD2
PWRGD3
EN2
LTC4253ACGN-ADJ LTC4253AIGN-ADJ
EN3
ORDER PART NUMBER
DRAIN
GATE
NC
VEE
OV
VEE 10
GN PACKAGE 20-LEAD PLASTIC SSOP
TJMAX = 125C, JA = 95C/W
Order Options Tape and Reel: Add #TR, Lead Free: Add #PBF, Lead Free Tape and Reel: Add #TRPBF, Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2)
SYMBOL VZ RZ IIN VLKO VLKH VIH VIL VHYST IRESET IEN PARAMETER VIN - VEE Zener Voltage VIN - VEE Zener Dynamic Impedance VIN Supply Current VIN Undervoltage Lockout VIN Undervoltage Lockout Hysteresis TTL Input High Voltage TTL Input Low Voltage TTL Input Buffer Hysteresis RESET Input Current EN2, EN3 Input Current VEE VRESET VIN VEN = 4V (Sinking) VEN = 0V

ELECTRICAL CHARACTERISTICS
CONDITIONS IIN = 2mA IIN = (2mA to 30mA) UV = UVL = OV = OVL = 4V, VIN = (VZ - 0.3V) Coming Out of UVLO (Rising VIN)

2
U
U
W
WW U
W
(Note 1) All voltages referred to VEE
Operating Temperature Range LTC4253A-ADJC ..................................... 0C to 70C LTC4253A-ADJI .................................. - 40C to 85C Storage Temperature Range SSOP ................................................ - 65C to 150C QFN .................................................. - 65C to 125C Lead Temperature (Soldering, 10 sec) SSOP ................................................................ 300C
TOP VIEW
ORDER PART NUMBER LTC4253ACUF-ADJ LTC4253AIUF-ADJ
20 19 18 17 16 VIN 1 RESET 2 SS 3 SEL 4 SENSE 5 6 7 8 9 10 21 15 SQTIMER 14 TIMER 13 UVL 12 UV 11 OVL
UF PART MARKING* 253AJ
UF PACKAGE 20-LEAD (4mm x 4mm) PLASTIC QFN
TJMAX = 125C, JA = 37C/W EXPOSED PAD (PIN 21) IS VEEMUST BE SOLDERED TO PCB
MIN 11.5
TYP 13 5 1.1 9
MAX 14.5 2 10 0.75 0.8
UNITS V mA V V V V mV A A A
4253a-adjf
0.25 2
0.5
600 0.1 60 120 0.1 10 180 10
LTC4253A-ADJ
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2)
SYMBOL ISEL VCB VACL VCB VFCL VSS ISS PARAMETER SEL Input Current Circuit Breaker Current Limit Voltage Analog Current Limit Voltage x% Circuit Breaker Current Limit Voltage Fast Current Limit Voltage SS Voltage SS Pin Current CONDITIONS VSEL = 0V (Sourcing) VSEL = VIN VCB = (VSENSE - VEE) VACL = (VSENSE - VEE), SS = Open or 1.4V VFCL = (VSENSE - VEE) After End of SS Timing Cycle UV = UVL = OV = OVL = 4V, VSENSE = VEE, VSS = 0V (Sourcing) UV = UVL = OV = OVL = 0V, VSENSE = VEE, VSS = 1V (Sinking) RSS VOS VACL + VOS VSS IGATE SS Output Impedance Analog Current Limit Offset Voltage Ratio (VACL + VOS) to SS Voltage GATE Pin Output Current UV = UVL = OV = OVL = 4V, VSENSE = VEE, VGATE = 0V (Sourcing) UV = UVL = OV = OVL = 4V, VSENSE - VEE = 0.15V, VGATE = 3V (Sinking) UV = UVL = OV = OVL = 4V, VSENSE - VEE = 0.3V, VGATE = 1V (Sinking) VGATE VGATEL VGATEH VUVHI VUVLO VOVHI VOVLO ISENSE IINP VTMRH VTMRL ITMR External MOSFET Gate Drive Gate Low Threshold Gate High Threshold UV Pin Threshold UVL Pin Threshold OV Pin Threshold OVL Pin Threshold SENSE Pin Input Current UV, UVL, OV, OVL Pin Input Current TIMER Pin Voltage High Threshold TIMER Pin Voltage Low Threshold TIMER Pin Current Timer On (Initial Cycle/Latchoff, Sourcing), VTMR = 2V Timer Off (Initial Cycle, Sinking), VTMR = 2V Timer On (Circuit Breaker, Sourcing, IDRN = 0A), VTMR = 2V Timer On (Circuit Breaker, Sourcing, IDRN = 50A), VTMR = 2V Timer Off (Circuit Breaker, Sinking), VTMR = 2V ITMRACC IDRN VSQTMRH VSQTMRL (ITMR at IDRN = 50A - ITMR at IDRN = 0A) 50A SQTIMER Pin Voltage High Threshold SQTIMER Pin Voltage Low Threshold Timer On (Circuit Breaker with IDRN = 50A)

ELECTRICAL CHARACTERISTICS
MIN 10 45 105 150 1.25 16
TYP 20 0.1 50 120 200 1.4 28 28 50 10 0.05
MAX 40 10 55 138 300 1.55 40
UNITS A A mV % mV V A mA k mV V/V
30
50 17 190
70
A mA mA
VGATE - VEE, IIN = 2mA (Before Gate Ramp Up) VGATEH = VIN - VGATE, For PWRGD1, PWRGD2, PWRGD3 Status UV Low to High UVL High to Low OV Low to High OVL High to Low UV = UVL = OV = OVL = 4V
10
12 0.5 2.8
VZ
V V V

3.05 3.05 5.04 5.025
3.08 3.08 5.09 5.08 15 0.1
3.11 3.11 5.14 5.135 30 1 4.5 1.2 7 280
V V V V A A V V A mA A A
UV = UVL = OV = OVL = 4V, VSENSE = 50mV (Sourcing) 3.5 0.8 3 120
4 1 5 28 200 600
3 7 3.5
5 8 4 0.33
7 9 4.5
A A/A V V
4253a-adjf
3
LTC4253A-ADJ
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2)
SYMBOL ISQTMR PARAMETER SQTIMER Pin Current CONDITIONS SQTIMER On (Power Good Sequence, Sourcing), VSQTMR = 2V SQTIMER On (Power Good Sequence, Sinking), VSQTMR = 2V VDRNL IDRNL VDRNCL VPGL IPGH tSQ tSS tPLLUG tPHLOG DRAIN Pin Voltage Low Threshold DRAIN Leakage Current DRAIN Pin Clamp Voltage PWRGD1, PWRGD2, PWRGD3 Signals Output Low Voltage PWRGD1, PWRGD2, PWRGD3 Output High Current SQ Timer Default Ramp Period SS Default Ramp Period UV Low to GATE Low OV High to GATE Low For PWRGD1, PWRGD2, PWRGD3 Status VDRAIN = 4V IDRN = 50A IPG = 1.6mA IPG = 5mA VPG = 0V (Sourcing) SQTIMER Pin Floating, VSQTMR Ramps from 0.5V to 3.5V SS Pin Floating, VSS Ramps from 0.2V to 1.25V

ELECTRICAL CHARACTERISTICS
MIN 3
TYP 5 28
MAX 7
UNITS A mA
2 5
2.39 0.1 6 0.25
3 1 7.5 0.4 1.2 70
V A V V V A s s
30
50 250 140 1 1
5 5
s s
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE unless otherwise specified.
TYPICAL PERFOR A CE CHARACTERISTICS
VZ vs Temperature
14.5 IIN = 2mA 14.0
IIN (mA)
10
IIN (mA)
13.5
VZ (V)
13.0
12.5
12.0 -50
-25
50 25 0 75 TEMPERATURE (C)
4
UW
100 125
4253A G01
IIN vs VIN
1000 TA = 125C TA = 85C TA = 25C TA = -40C
1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6
IIN vs Temperature
VIN = VZ - 0.3V
100
1
0.1
0
5
10 VIN (V)
15
20
4253A G02
0.5 -50 -25
50 25 0 75 TEMPERATURE (C)
100
125
4253A G03
4253a-adjf
LTC4253A-ADJ TYPICAL PERFOR A CE CHARACTERISTICS
IEN vs VEN and ISEL vs VSEL
200
55
IIN = 2mA TA = 25C IEN
160
IEN/ISEL (A)
VCB (mV)
120
50 49 48
VACL (mV)
80
40
ISEL
0 0 2 4 6 8 10 12 VEN/VSEL (V) 14 16 18
Fast Current Limit Voltage VFCL vs Temperature
250 240 230 220
VFCL (mV) IGATE (A)
IIN = 2mA
200 190 180 170 160 150 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
50 48 46 44 42 40 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
IGATE (mA)
210
IGATE (FCL, Sink) vs Temperature
250
14.5 14.0
200
IGATE (mA)
12.5 12.0 11.5 11.0 10.5
VGATEL (V)
VGATE (V)
150
100 IIN = 2mA UV/UVL/OV/OVL = 4V TIMER = 0V VSENSE - VEE = 0.3V VGATE = 1V 50 25 0 75 TEMPERATURE (C) 100 125
50
0 -50 -25
UW
4253A G04
Circuit Breaker Current Limit Voltage VCB vs Temperature
54 53 52 51 IIN = 2mA
Analog Current Limit Voltage VACL vs Temperature
80 75 70 65 60 55 50 45 IIN = 2mA
47 46 45 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
40 -50 -25
0
50 75 25 TEMPERATURE (C)
100
125
4253A G05
4253A G06
IGATE (Source) vs Temperature
60 58 56 54 52 IIN = 2mA UV/UVL/OV/OVL = 4V TIMER = 0V VSENSE = VEE VGATE = 0V
IGATE (ACL, Sink) vs Temperature
30 25 20 15 10 5 0 -50 -25 IIN = 2mA UV/UVL/OV/OVL = 4V TIMER = 0V VSENSE - VEE = 0.15V VGATE = 3V
50 25 75 0 TEMPERATURE (C)
100
125
4253A G07
4253A G08
4253A G09
VGATE vs Temperature
IIN = 2mA UV/UVL/OV/OVL = 4V TIMER = 0V VSENSE = VEE 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 -25 0 25 50 75 TEMPERATURE (C) 100 125
VGATEL vs Temperature
IIN = 2mA UV/UVL/OV/OVL = 4V TIMER = 0V GATE THRESHOLD BEFORE RAMP UP
13.5 13.0
10.0 -50
0 -50 -25
50 25 0 75 TEMPERATURE (C)
100
125
4253A G10
4253A G11
4253A G12
4253a-adjf
5
LTC4253A-ADJ TYPICAL PERFOR A CE CHARACTERISTICS
VGATEH vs Temperature
3.6 IIN = 2mA UV/UVL/OV/OVL = 4V 3.4 VGATEH = VIN - VGATE 3.2
UV THRESHOLD (V)
VGATEH (V)
3.0 2.8 2.6 2.4 2.2 2.0 -50 -25 0 50 75 25 TEMPERATURE (C) 100 125
3.09 VUVHI AND VUVLO 3.08 3.07 3.06 3.05 -50 -25
0V THRESHOLD (V)
ISENSE vs (VSENSE - VEE)
0.01
0 -5 -10
0.1
TIMER THRESHOLD (V)
-ISENSE (mA)
1
ISENSE (A)
10 IIN = 2mA UV/UVL/OV/OVL = 4V TIMER = 0V GATE = HIGH TA = 25C -1 -0.5 0 0.5 VSENSE - VEE (V) 1 1.5
4253A G16
100
1000 -1.5
ITMR (Initial Cycle, Sourcing) vs Temperature
10 9 8 7
ITMR (A)
ITMR (A)
IIN = 2mA VTMR = 2V
ITMR (mA)
6 5 4 3 2 1 0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
6
UW
4253A G13
UV Threshold vs Temperature
3.11 3.10 IIN = 2mA 5.14 5.12 5.10 5.08 5.06 5.04
OV Threshold vs Temperature
IIN = 2mA
VOVHI VOVLO
50 25 75 0 TEMPERATURE (C)
100
125
5.02 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
4253A G14
4253A G15
ISENSE vs Temperature
IIN = 2mA UV/UVL/OV/OVL = 4V TIMER = 0V VSENSE - VEE = 50mV VGATE = HIGH
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5
TIMER Threshold vs Temperature
IIN = 2mA
VTMRH
-15 -20 -25 -30 -50 -25
VTMRL
50 25 75 0 TEMPERATURE (C)
100
125
0 -50 -25
50 25 0 75 TEMPERATURE (C)
100
125
4253A G17
4253A G18
ITMR (Circuit Breaker, Sourcing) vs Temperature
240 230 220 210 200 190 180 170 160 -50 -25 0 50 75 25 TEMPERATURE (C) 100 125
10
ITMR vs IDRN
IIN = 2mA TA = 25C
IIN = 2mA IDRN = 0A
1
0.1 0.001
0.01
0.1 IDRN (mA)
1
10
4253A G21
4253A G19
4253A G20
4253a-adjf
LTC4253A-ADJ TYPICAL PERFOR A CE CHARACTERISTICS
ITMRACC/IDRN vs Temperature
9.0 8.8 8.6 4.5 IIN = 2mA 4.0 3.5 3.0
ITMRACC/IDRN (A/A)
8.4 8.2 8.0 7.8 7.6 7.4 7.2 7.0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
VSQTMR (V)
2.5 2.0 1.5 1.0 0.5 0 -50 -25 VSQTMRL 0 25 50 75 TEMPERATURE (C) 100 125
VDRNL (V)
VDRNCL vs Temperature
7.0 6.8 6.6 6.4
VDRNCL (V)
IDRN (mA)
IIN = 2mA IDRN = 50A
0.01 0.001 0.0001
6.0 5.8 5.6 5.4 5.2 5.0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
VPGL (V)
6.2
IPGH vs Temperature
60 58 56 54 IIN = 2mA VPWRGD = 0V 200 190 180 170
IPGH (A)
50 48 46 44 42 40 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
150 140 130 120 110 100 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
tSQ (s)
tSS (s)
52
UW
4253A G22
SQTIMER Threshold vs Temperature
IIN = 2mA VSQTMRH
VDRNL vs Temperature
2.60 2.55 2.50 2.45 2.40 2.35 2.30 2.25 2.20 -50 -25 0 50 75 25 TEMPERATURE (C) 100 125 IIN = 2mA
4253A G23
4253A G24
IDRN vs VDRAIN
100 10 1 0.1
1.5 2.0
VPGL vs Temperature
2.2 IIN = 2mA
IIN = 2mA
IPG = 10mA
1.0
IPG = 5mA IPG = 1.6mA
0.00001 0.0000001 0.00000001 1 2 4 8 10 6 VDRAIN (V)
TA = 125C TA = 85C TA = 25C TA = -40C 12 14 16
0.5
0 -50
-25
50 25 0 75 TEMPERATURE (C)
100
125
4253A G25
4253A G26
4253A G27
tSS vs Temperature
IIN = 2mA SS PIN FLOATING VSS RAMPS FROM 0.2V TO 1.25V 300 290 280 270 260 250 240 230 220 210
tSQ vs Temperature
IIN = 2mA SQTMR PIN FLOATING VSQTMR RAMPS FROM 0.5V TO 3.5V
160
200 -50 -25
50 25 0 75 TEMPERATURE (C)
100
125
4253A G28
4253A G29
4253A G30
4253a-adjf
7
LTC4253A-ADJ
PI FU CTIO S U U U
(SSOP/QFN)
EN2 (Pin 1/Pin 18): Power Good Status Output Two Enable. This is a TTL compatible input that is used to control PWRGD2 and PWRGD3 outputs. When EN2 is driven low, both PWRGD2 and PWRGD3 will go high. When EN2 is driven high, PWRGD2 will go low provided PWRGD1 has been active for more than one power good sequence delay (tSQT) provided by the sequencing timer. EN2 can be used to control the power good sequence. This pin is internally pulled low by a 120A current source. PWRGD2 (Pin 2/Pin 19): Power Good Status Output Two. Power good sequence starts with DRAIN going below 2.39V and GATE is within 2.8V on VIN. PWRGD2 will latch active low after EN2 goes high and after one power good sequence delay tSQT provided by the sequencing timer from the time PWRGD1 goes low, whichever comes later. PWRGD2 is reset by PWRGD1 going high or EN2 going low. This pin is internally pulled high by a 50A current source. PWRGD1 (Pin 3/Pin 20): Power Good Status Output One. At start-up, PWRGD1 latches active low one tSQT after both DRAIN is below 2.39V and GATE is within 2.8V of VIN. PWRGD1 status is reset by undervoltage, VIN (UVLO), RESET going high or circuit breaker fault time-out. This pin is internally pulled high by a 50A current source. VIN (Pin 4/Pin 1): Positive Supply Input. Connect this pin to the positive side of the supply through a dropping resistor. A shunt regulator clamps VIN at 13V above VEE. An internal undervoltage lockout (UVLO) circuit holds GATE low until the VIN pin is greater than VLKO (9V), overriding undervoltage and overvoltage events. If there is no undervoltage, no overvoltage and VIN comes out of UVLO, TIMER starts an initial timing cycle before initiating GATE ramp up. If VIN drops below approximately 8.5V, GATE pulls low immediately. RESET (Pin 5/Pin 2): Circuit Breaker Reset Pin. This is an asynchronous TTL compatible input. RESET going high will pull GATE, SS, TIMER, SQTIMER low and the PWRGD outputs high. The RESET pin has an internal glitch filter that rejects any pulse < 20s. After the reset of a latched fault, the chip waits for the interlock conditions before recovering as described in Interlock Conditions in the Operation section.
SS (Pin 6/Pin 3): Soft-Start Pin. This pin is used to ramp inrush current during start up, thereby effecting control over di/dt. A 20X attenuated version of the SS pin voltage is presented to the current limit amplifier. This attenuated voltage limits the MOSFET's drain current through the sense resistor during the soft-start current limiting. At the beginning of the start-up cycle, the SS capacitor (CSS) is ramped by a 28A current source. The GATE pin is held low until SS exceeds 20 * VOS = 0.2V. SS is internally shunted by a 50k RSS which limits the SS pin voltage to 1.4V. This corresponds to an analog current limit SENSE voltage of 60mV. SEL (Pin 7/Pin 4): Soft-Start Mode Select. This is an asynchronous TTL compatible input. SEL has an internal pull-up of 20A that will pull it high if it is floated. SEL selects between two modes of SS ramp-up (see Applications Information, Soft-Start section). SENSE (Pin 8/Pin 5): Circuit Breaker/Current Limit Sense Pin. Load current is monitored by a sense resistor RS connected between SENSE and VEE, and controlled in three steps. If SENSE exceeds VCB (50mV), the circuit breaker comparator activates a (200A + 8 * IDRN) TIMER pull-up current. If SENSE exceeds VACL (60mV), the analog current-limit amplifier pulls GATE down to regulate the MOSFET current at VACL/RS. In the event of a catastrophic short-circuit, SENSE may overshoot VACL. If SENSE reaches VFCL (200mV), the fast current-limit comparator pulls GATE low with a strong pull-down. To disable the circuit breaker and current limit functions, connect SENSE to VEE. VEE (Pins 9, 10/Pin 7): Negative Supply Voltage Input. Connect this pin to the negative side of the power supply. GATE (Pin 11/Pin 8): N-channel MOSFET Gate Drive Output. This pin is pulled high by a 50A current source. GATE is pulled low by invalid conditions at VIN (UVLO), undervoltage, overvoltage, during the initial timing cycle, a circuit breaker fault time-out or the RESET pin going high. GATE is actively servoed to control the fault current as measured at SENSE. Compensation capacitor, CC, at GATE stabilizes this loop. A comparator monitors GATE to ensure that it is low before allowing an initial timing cycle, then the GATE ramps up after an overvoltage event or
4253a-adjf
8
LTC4253A-ADJ
PI FU CTIO S
restart after a current limit fault. During GATE start-up, a second comparator detects GATE within 2.8V of VIN before power good sequencing starts. DRAIN (Pin 12/Pin 9): Drain Sense Input. Connecting an external resistor, RD between this pin and the MOSFET's drain (VOUT) allows voltage sensing below 5V and current feedback to TIMER. A comparator detects if DRAIN is below 2.39V and together with the GATE high comparator, starts the power good sequencing. If VOUT is above VDRNCL, the DRAIN pin is clamped at approximately VDRNCL. RD current is internally multiplied by 8 and added to TIMER's 200A during a circuit breaker fault cycle. This reduces the fault time and MOSFET heating. OV/OVL (Pins 13, 14/Pins 10, 11): Overvoltage and Overvoltage Low Inputs. The OV and OVL pins work together to implement the overvoltage function. OVL and OV must be tapped from an external resistive string across the input supply such that VOVL VOV under all circumstances. As the input supply ramps up, the OV pin input is multiplexed to the internal overvoltage comparator input. If OV > 5.09V, GATE pulls low and the overvoltage comparator input is switched to OVL. When OVL returns below 5.08V, GATE start-up begins without an initial timing cycle and the overvoltage comparator input is switched to OV. In this way, an external resistor between OVL and OV can set a low to high and high to low overvoltage threshold hysteresis that will add to the internal 10mV hysteresis. A 1nF to 10nF capacitor at OVL prevents transients and switching noise at both OVL and OV from causing glitches at the GATE. UV/UVL (Pins 15, 16/Pins 12, 13): Undervoltage and Undervoltage Low Inputs. The UV and UVL pins work together to implement the undervoltage function. UVL and UV must be tapped from an external resistive string across the input supply such that VUVL VUV under all circumstances. As the input supply ramps up, the UV pin input is multiplexed to the internal undervoltage comparator input. If UV > 3.08V, an initial timing cycle is initiated
U
U
U
(SSOP/QFN)
followed by GATE start-up and input to the undervoltage comparator input is switched to UVL. When UVL returns below 3.08V, PWRGD1 pulls high, both GATE and TIMER pull low and input to the undervoltage comparator input is switched to UV. In this way, an external resistor between UVL and UV can set the low to high and high to low undervoltage threshold hysteresis. A 1nF to 10nF capacitor at UVL prevents transients and switching noise at both UVL and UV from causing glitches at the GATE pin. TIMER (Pin 17/Pin 14): Timer Input. Timer is used to generate an initial timing delay at start-up, and to delay shutdown in the event of an output overload (circuit breaker fault). These delays are adjustable by connecting an appropriate capacitor to this pin. SQTIMER (Pin 18/Pin 15): Sequencing Timer Input. The sequencing timer provides a delay tSQT for the power good sequencing. This delay is adjusted by connecting an appropriate capacitor to this pin. If the SQTIMER capacitor is omitted, the SQTIMER pin ramps from 0V to 4V in about 300s. EN3 (Pin 19/Pin 16): Power Good Status Output Three Enable. This is a TTL compatible input that is used to control the PWRGD3 output. When EN3 is driven low, PWRGD3 will go high. When EN3 is driven high, PWRGD3 will go low provided PWRGD2 has been active for for more than one power good sequence delay (tSQT). EN3 can be used to control the power good sequence. This pin is internally pulled low by a 120A current source. PWRGD3 (Pin 20/Pin 17): Power Good Status Output Three. Power good sequence starts with DRAIN going below 2.39V and GATE is within 2.8V of VIN. PWRGD3 will latch active low after EN3 goes high and after one power good sequence delay tSQT provided by the sequencing timer from the time PWRGD2 goes low, whichever comes later. PWRGD3 is reset by PWRGD1 going high or EN3 going low. This pin is internally pulled high by a 50A current source.
4253a-adjf
9
LTC4253A-ADJ
BLOCK DIAGRA
VIN 50A PWRGD1 SQTIMER DELAY VEE EN2 VIN 120A 50A PWRGD2 SQTIMER DELAY VEE EN3 VIN 120A 50A PWRGD3 SQTIMER DELAY VEE VEE VIN 50A GATE VIN VEE VEE VEE VEE
OVL
OV
UVL
UV VIN 200A VIN
TIMER
VEE VIN 28A VEE
SS VOS = 10mV 47.5k RSS 2.5k VIN VEE VEE 20A CB
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VIN VIN
- +
4V
5A
SQTIMER
- + -
VIN 0.33V VEE
DRAIN
+
2.39V
8x
1x
5V
1x
1x
5.09V OVIN
- +
OVD
- +
+ -
2.8V
UVIN
- +
UVD LOGIC
- +
0.5V
3.08V
5A 4V
-
FCL
+ - + -
200mV
+
-
5A 1V
VEE
+ +
ACL
- + -
VEE
+ - + -
VEE
4253A BD
SENSE
50mV
SEL
RESET
VEE
4253a-adjf
LTC4253A-ADJ
OPERATIO
Hot Circuit Insertion When circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient currents from the power bus as they charge. The flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset. The LTC4253A-ADJ is designed to turn on a circuit board supply in a controlled manner, allowing insertion or removal without glitches or connector damage. Initial Start-Up The LTC4253A-ADJ resides on a removable circuit board and controls the path between the connector and load or power conversion circuitry with an external MOSFET switch. Both inrush control and short-circuit protection are provided by the MOSFET. A detailed schematic is shown in Figure 1. - 48V and - 48RTN receive power through the longest connector pins and are the first to connect when the board is inserted. The GATE pin holds the MOSFET off during this time. UV/UVL/OV/OVL determines whether or not the MOSFET should be turned on based upon internal high accuracy thresholds and an external divider. UV/UVL/OV/ OVL does double duty by also monitoring whether or not the connector is seated. The top of the divider detects
- 48V RTN (LONG PIN) RESET (LONG PIN) - 48V RTN (SHORT PIN) 294k 1% 2.74k 1% R4 2.37k 1% R3 2.1k 1% R2 0.976k 1% C1 10nF CSS 33nF R1 20k 1% - 48V (LONG PIN) OV SS SQTIMER CSQ 0.1F TIMER SEL CT 0.68F RIN 2.5k 15k(1/4W)/6 CIN 1F R5 RESET UVL UV OVL VIN R6 5.6k
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- 48RTN by way of a short connector pin that is the last to mate during the insertion sequence. Interlock Conditions A start-up sequence commences once these "interlock" conditions are met: 1. The input voltage VIN exceeds VLKO (UVLO) 2. The voltage at UV > VUVHI 3. The voltage at OVL < VOVLO 4. The input voltage at RESET < 0.8V 5. The (SENSE - VEE) voltage < 50mV (VCB) 6. The voltage at SS is < 0.2V (20 * VOS) 7. The voltage on the TIMER capacitor (CT) is < 1V (VTMRL) 8. The voltage at GATE is < 0.5V (VGATEL) The first four conditions are continuously monitored and the latter four are checked prior to initial timing or GATE ramp-up. Upon exiting an overvoltage condition, the TIMER pin voltage requirement is inhibited. Details are described in the Applications Information, Timing Waveforms section.
VIN R7 5.6k R8 5.6k
+
POWER CL 100F MODULE 1 EN
POWER MODULE 2 EN
POWER MODULE 3 EN
LTC4253A-ADJ

PWRGD1 PWRGD2 PWRGD3 EN3 EN2 DRAIN GATE SENSE VEE CC 10nF RC 10 Q1 IRF530S VIN POWER MODULE 1 OUTPUT RD 1M EN3 EN2 VIN POWER MODULE 2 OUTPUT
RS 0.02
MOC207
4253A F01
Figure 1. - 48V/2.5A Application with Operating Range from 43V to 82V
4253a-adjf
11
LTC4253A-ADJ
OPERATIO
If RESET < 0.8V occurs after the LTC4253A-ADJ comes out of UVLO (interlock condition 1) and undervoltage (interlock condition 2), GATE and SS are released without an initial TIMER cycle once the other interlock conditions are met (see Figure 13a). If not, TIMER begins the start-up sequence by sourcing 5A into CT. If VIN, UVL/UV or OVL/ OV falls out of range or RESET asserts, the start-up cycle stops and TIMER discharges CT to less than 1V, then waits until the aforementioned conditions are once again met. If CT successfully charges to 4V, TIMER pulls low and both SS and GATE pins are released. GATE sources 50A (IGATE), charging the MOSFET gate and associated capacitance. The SS voltage ramp limits VSENSE to control the inrush current. The SEL pin selects between two different modes of SS ramp-up (refer to Applications Information, Soft-Start section). SQTIMER starts its ramp-up when GATE is within 2.8V of VIN and DRAIN is lower than VDRNL. This sets off the power good sequence in which PWRGD1, PWRGD2 and then PWRGD3 is subsequently pulled low after a delay, adjustable through the SQTIMER capacitor CSQ or by external control inputs EN2 and EN3. In this way, external loads or power modules controlled by the three PWRGD signals are turned on in a controlled manner without overloading the power bus. Two modes of operation are possible during the time the MOSFET is first turned on, depending on the values of external components, MOSFET characteristics and nominal design current. One possibility is that the MOSFET will turn on gradually so that the inrush into the load capacitance remains a low value. The output will simply ramp to - 48V and the LTC4253A-ADJ will fully enhance the MOSFET. A second possibility is that the load current exceeds the softstart current limit threshold of [VSS(t)/20 - VOS]/RS. In this case the LTC4253A-ADJ will ramp the output by sourcing soft-start limited current into the load capacitance. If the soft-start voltage is below 1.2V, the circuit breaker TIMER is held low. Above 1.2V, TIMER ramps up. It is important to set the timer delay so that, regardless of which start-up mode is used, the TIMER ramp is less than one circuit breaker delay time. If this condition is not met, the LTC4253A-ADJ may shut down after one circuit breaker delay time.
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Board Removal When the board is withdrawn from the card cage, the UVL/ UV/OVL/OV divider is the first to lose connection. This shuts off the MOSFET and commutates the flow of current in the connector. When the power pins subsequently separate there is no arcing. Current Control Three levels of protection handle short-circuit and overload conditions. Load current is monitored by SENSE and resistor RS. There are three distinct thresholds at SENSE: 50mV for a timed circuit breaker function; 60mV for an analog current limit loop; and 200mV for a fast, feedforward comparator which limits peak current in the event of a catastrophic short-circuit. If, due to an output overload, the voltage drop across RS exceeds 50mV, TIMER sources 200A into CT. CT eventually charges to a 4V threshold and the LTC4253A-ADJ shuts off. If the overload goes away before CT reaches 4V and SENSE measures less than 50mV, CT slowly discharges (5A). In this way the LTC4253A-ADJ's circuit breaker function responds to low duty cycle overloads, and accounts for the fast heating and slow cooling characteristic of the MOSFET. Higher overloads are handled by an analog current limit loop. If the drop across RS reaches VACL, the current limiting loop servos the MOSFET gate and maintains a constant output current of VACL/RS. In current limit mode, VOUT (MOSFET drain-source voltage drop) typically rises and this increases MOSFET heating. If VOUT > VDRNCL, connecting an external resistor, RD between VOUT and DRAIN allows the fault timing cycle to be shortened by accelerating the charging of the TIMER capacitor. The TIMER pull-up current is increased by 8 * IDRN. Note that because SENSE > 50mV, TIMER charges CT during this time, and the LTC4253A-ADJ will eventually shut down. Low impedance failures on the load side of the LTC4253AADJ coupled with 48V or more driving potential can produce current slew rates well in excess of 50A/s. Under these conditions, overshoot is inevitable. A fast SENSE
4253a-adjf
LTC4253A-ADJ
OPERATIO
comparator with a threshold of 200mV detects overshoot and pulls GATE low much harder and hence much faster than the weaker current limit loop. The VACL/RS current limit loop then takes over, and servos the current as previously described. As before, TIMER runs and shuts down LTC4253A-ADJ when CT reaches 4V. If CT reaches 4V, the LTC4253A-ADJ latches off with a 5A pull-up current source. The LTC4253A-ADJ circuit breaker latch is reset by either pulling the RESET pin active high for >20s, pulling UVL/UV momentarily low, dropping the input voltage VIN below the internal UVLO threshold or pulsing TIMER momentarily low with a switch.
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Although short-circuits are the most obvious fault type, several operating conditions may invoke overcurrent protection. Noise spikes from the backplane or load, input steps caused by the connection of a second, higher voltage supply, transient currents caused by faults on adjacent circuit boards sharing the same power bus or the insertion of non-hot swappable products could cause higher than anticipated input current and temporary detection of an overcurrent condition. The action of TIMER and CT rejects these events allowing the LTC4253A-ADJ to "ride out" temporary overloads and disturbances that could trip a simple current comparator and, in some cases, blow a fuse.
4253a-adjf
13
LTC4253A-ADJ
APPLICATIO S I FOR ATIO
SHUNT REGULATOR
A fast responding regulator shunts the LTC4253A-ADJ VIN pin. Power is derived from -48RTN by an external current limiting resistor. The shunt regulator clamps VIN to 13V (VZ). A 1F decoupling capacitor at VIN filters supply transients and contributes a short delay at start-up. RIN should be chosen to accommodate both VIN supply current and the drive required for three optocouplers used by the PWRGD signals. Higher current through RIN results in higher dissipation for RIN and LTC4253A-ADJ as well as higher VIN noise. Alternative circuits are VIN with an NPN buffer as in Figure 16, VIN driving base resistors of NPN cascodes as in Figure 17 or VIN driving the gates of MOSFET cascodes replacing the NPNs in Figure 17. An alternative is a separate NPN buffer driving the optocoupler as shown in Figure 16. Multiple 1/4W resistors can replace a single higher power RIN resistor. INTERNAL UNDERVOLTAGE LOCKOUT (UVLO) A hysteretic comparator, UVLO, monitors VIN for undervoltage. The thresholds are defined by VLKO and its hysteresis VLKH. When VIN rises above VLKO the chip is
1 2 3 4
VIN
VLKO 36V (UNDERVOLTAGE SHUTDOWN VOLTAGE)
(-48V RTN) SHORT PIN
38V (UNDERVOLTAGE RECOVERY VOLTAGE)
VUVHI 3.08V UVL UV
VUVLO 3.08V OVL OV
UVD
UVIN
UVL
UV
UVLO
UNDERVOLTAGE SHUTDOWN
NORMAL OPERATION
UNDERVOLTAGE SHUTDOWN
(2a) Undervoltage
Figure 2. Undervoltage/Overvoltage Recovery and Shutdown (All Waveforms are Referenced to VEE)
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U
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(Refer to Block Diagram)
enabled; below (VLKO - VLKH) it is disabled and GATE is pulled low. The UVLO function at VIN should not be confused with the UVL/UV and OVL/OV pins. These are completely separate functions. UNDERVOLTAGE AND OVERVOLTAGE COMPARATORS The undervoltage comparator has inputs multiplexed from UVL and UV. When comparator output UVD is high, UV is multiplexed to the comparator input UVIN. When UVD is low, UVL is multiplexed to UVIN. By tapping UVL and UV off a resistive string across the supply such as in the Typical Application, the undervoltage function is implemented as shown in Figure 2a. During UVLO, UVD is forced high so UV is multiplexed to UVIN. At time point 1, VIN ramps past VLKO and the undervoltage comparator is enabled. UVIN = UV is less than VUVHI (3.08V), so UVD is high and the part is in undervoltage shutdown. At time point 2, UV ramps past VUVHI (3.08V) and UVD goes low, bringing the part out of undervoltage and switching UVL to UVIN. UVL is tied to UVIN until time point 3 when UVL ramps past VUVLO (3.08V) and UVD goes high, bringing the part into undervoltage shutdown and switching UV to UVIN.
1 2 3 4
VIN
VLKO 69V (OVERVOLTAGE RECOVERY VOLTAGE)
(-48V RTN) SHORT PIN
71V (OVERVOLTAGE SHUTDOWN VOLTAGE)
VOVHI 5.09V
VOVLO 5.08V
OVD
OVIN
0VL
OV
4253A F02
UVLO
NORMAL OPERATION
OVERVOLTAGE SHUTDOWN
NORMAL OPERATION
(2b) Overvoltage
4253a-adjf
LTC4253A-ADJ
APPLICATIO S I FOR ATIO
Figure 2b shows the implementation of the overvoltage function of the Typical Application. During UVLO, OVD is forced high so OVL is multiplexed to OVIN. At time point 1, the part exits UVLO and the overvoltage comparator is enabled. OVIN = OVL is less than VOVLO (5.08V) so OVD goes low, switching OV to OVIN and bringing the part to Normal mode. At time point 2, OV ramps past VOVHI (5.09V) and OVD goes high, switching OVL to OVIN as well as turning on the internal 10mV hysteresis as the part goes into overvoltage. OVL is tied to OVIN until time point 3 when OVL ramps past VOVLO (5.09V - 10mV = 5.08V) and OVD goes low, bringing the part into Normal mode and switching OV to OVIN. The undervoltage (UV) comparator has no internal hysteresis to preserve the accuracy of the hysteresis set across UVL/UV while the overvoltage (OV) comparator has an internal low to high hysteresis of 10mV. This will add to the hysteresis set across OVL/OV and provide some noise immunity if OVL/OV is shorted together. Any implementation must ensure that VUVL VUV and VOVL VOV under all conditions. The various thresholds to note are: UV low-to-high (VUVHI) = 3.08V UVL high-to-low (VUVLO) = 3.08V OV low-to-high (VOVHI) = 5.09V OVL high-to-low (VOVLO) = 5.08V Using these thresholds and an external resistive divider, any required supply operating range can be implemented. An example is shown in Figure 1 where the required typical operating range is: Undervoltage low-to-high (V48UVHI) = 43V Undervoltage high-to-low (V48UVLO) = 39V Overvoltage low-to-high (V48OVHI) = 82V Overvoltage high-to-low (V48OVLO) = 78V A quick check of the resistive divider ratios required at UVL, UV, OVL and OV confirms that UVL is tapped between R5/R4, UV is tapped between R4/R3, OVL is tapped between R3/R2 and OV is tapped between R2/R1.
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From Figure 1, by looking at the voltages at OV, OVL, UV and UVL, the following equations are obtained:
RTOTAL V48OVHI = R1 VOVHI where: RTOTAL = (R1 + R2 + R3 + R4 + R5) RTOTAL = R1 * V48OVHI VOVHI
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(1a)
RTOTAL V48OVLO = R1 + R2 VOVLO V V R2 = R1 OVLO * 48OVHI - R1 V48OVLO VOVHI
(1b)
RTOTAL V = 48UVHI R1 + R2 + R3 VUVHI V V R3 = R1 UVHI * 48OVHI - R1 - R2 V48UVHI VOVHI RTOTAL V = 48UVLO R1 + R2 + R3 + R4 VUVLO V V R4 = R1 UVLO * 48OVHI - R1 - R2 - R3 V48UVLO VOVHI
(1c)
(1d)
Starting with a value of 20k for R1, Equation 1b gives R2 = 0.984k (use closest 1% standard value of 0.976k). Using R1 = 20k and R2 = 0.976k, Equation 1c gives R3 = 2.103k (use the closest 1% standard value of 2.1k). Using R1 = 20k, R2 = 0.976k and R3 = 2.1k, Equation 1d gives R4 = 2.37k (use closest 1% standard value of 2.37k). Using R1 = 20k, R2 = 0.976k, R3 = 2.1k and R4 = 2.37k in Equation 1a, R5 = 296.754k (use 1% standard values of 294k in series with 2.74k). The divider values shown set a standing current of slightly more than 150A and define an impedance at UVL/UV/ OVL/OV of approximately 20k. This impedance will work with the hysteresis set across UVL/UV and OVL/OV to provide noise immunity to the UV and OV comparators. If
4253a-adjf
15
LTC4253A-ADJ
APPLICATIO S I FOR ATIO
more noise immunity is desired, add a 1nF to 10nF filter capacitor from UVL to VEE. UV/OV OPERATION An undervoltage condition detected by the UV comparator immediately shuts down the LTC4253A-ADJ, pulls GATE, SS and TIMER low and resets the three latched PWRGD signals high. Recovery from an undervoltage will initiate an initial timing sequence if the other interlock conditions are met. An overvoltage condition is detected by the OV comparator and pulls GATE low, thereby shutting down the load, but it will not reset the circuit breaker TIMER and PWRGD flags. Returning from the overvoltage condition will restart the GATE pin if all the interlock conditions except TIMER are met. Only during the initial timing cycle does an overvoltage condition have an effect of resetting TIMER. The internal UVLO at VIN always overrides an overvoltage or undervoltage. DRAIN Connecting an external resistor, RD, to this dual function DRAIN pin allows VOUT (MOSFET drain-source voltage drop) sensing without it being damaged by large voltage transients. Below 5V, negligible pin leakage allows a DRAIN low comparator to detect VOUT less than 2.39V (VDRNL). This, together with the GATE low comparator, starts the power good sequencing. When VOUT > VDRNCL, the DRAIN pin is clamped at VDRNCL and the current flowing in RD is given by:
IDRN
VOUT - VDRNCL RD
This current is scaled up 8 times during a circuit breaker fault before being added to the nominal 200A. This accelerates the fault TIMER pull-up when the MOSFET's drain-source voltage exceeds VDRNCL and effectively shortens the MOSFET heating duration. TIMER The operation of the TIMER pin is somewhat complex as it handles several key functions. A capacitor CT is used at
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TIMER to provide timing for the LTC4253A-ADJ. Four different charging and discharging modes are available at TIMER: 1. 5A slow charge; initial timing delay. 2. (200A + 8 * IDRN) fast charge; circuit breaker delay. 3. 5A slow discharge; circuit breaker "cool-off." 4. Low impedance switch; resets the TIMER capacitor after an initial timing delay, in UVLO, in UV and in OV during initial timing and when RESET is high. For initial timing delay, the 5A pull-up is used. The low impedance switch is turned off and the 5A current source is enabled when the interlock conditions are met. CT charges to 4V in a time period given by:
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t=
4V * C T 5A
(3)
When CT reaches VTMRH (4V), the low impedance switch turns on and discharges CT. A GATE start-up cycle begins and both SS and GATE outputs are released. CIRCUIT BREAKER TIMER OPERATION If the SENSE pin detects more than 50mV drop across RS, the TIMER pin charges CT with (200A + 8 * IDRN). If CT charges to 4V, the GATE pin pulls low and the LTC4253A-ADJ latches off. The LTC4253A-ADJ remains latched off until the RESET pin is momentarily pulsed high, the UVL/UV pin is momentarily pulsed low, the TIMER pin is momentarily discharged low by an external switch or VIN dips below UVLO and is then restored. The circuit breaker timeout period is given by:
t= 4V * C T 200A + 8 * IDRN
(2) (4)
If VOUT < 5V, an internal PMOS isolates DRAIN pin leakage current and this makes IDRN = 0 in Equation 4. If VOUT is above VDRNCL during the circuit breaker fault period, the charging of CT is accelerated by 8 * IDRN of Equation 2. Intermittent overloads may exceed the 50mV threshold at SENSE but, if their duration is sufficiently short, TIMER will not reach 4V and the LTC4253A-ADJ will not shut the
4253a-adjf
LTC4253A-ADJ
APPLICATIO S I FOR ATIO
external MOSFET off. To handle this situation, the TIMER discharges CT slowly with a 5A pull-down whenever the SENSE voltage is less than 50mV. Therefore any intermittent overload with VOUT < 5V and an aggregate duty cycle of more than 2.5% will eventually trip the circuit breaker and shut down the LTC4253A-ADJ. Figure 3 shows the circuit breaker response time in seconds normalized to 1F. The asymmetric charging and discharging of CT is a fair gauge of MOSFET heating. The normalized circuit response time is estimated by:
t 4 for D > 2.5% (5) = CT (F ) (205 + 8 * IDRN ) * D - 5
[
]
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NORMALIZED RESPONSE TIME (s/F)
IDRN = 0A
1
4 t = CT(F) (205 + 8 * IDRN) * D - 5
0.1
0.01
0
20 40 60 80 FAULT DUTY CYCLE, D (%)
100
4253A F03
Figure 3. Circuit Breaker Response Time
POWER GOOD SEQUENCING After the initial TIMER cycle, GATE ramps up to turn on the external MOSFET which in turn pulls DRAIN low. When GATE is within 2.8V of VIN and DRAIN is lower than VDRNL, the power good sequence starts off a 5A pull-up on the SQTIMER pin which ramps up until it reaches the 4V threshold then pulls low. When the SQTIMER pin floats, this delay tSQT is about 300s. Connecting an external capacitor CSQ from SQTIMER to VEE modifies the delay to:
tSQT =
4V * C SQ 5A
PWRGD1 asserts low after one tSQT and SQTIMER ramps up on another delay cycle. PWRGD2 asserts when EN2 goes high and PWRGD1 has asserted for more than one
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tSQT. When PWRGD2 successfully pulls low, SQTIMER ramps up on another delay cycle. PWRGD3 asserts when EN2 and EN3 go high and PWRGD2 has asserted for more than one tSQT. All three PWRGD signals are reset in UVLO, in UV condition, if RESET is high or when CT charges up to 4V. In addition, PWRGD2 is reset by EN2 going low. PWRGD3 is reset by EN2 or EN3 going low. An overvoltage condition has no effect on the PWRGD flags. A 50A current pulls each PWRGD pin high when reset. As power modules signal common are different from PWRGD, optoisolation is recommended. These three pins can sink an optodiode current. Figure 17 shows an NPN configuration for the PWRGD interface. A limiting base resistor should be used for each NPN and the module enable input should have protection from negative bias current. Figure 17 also shows how the LTC4253A-ADJ can be used to sequence four power modules. SOFT-START Soft-start is effective in limiting the inrush current during GATE start-up. From the Block Diagram, the internal SS circuit consists of a current ISS (28A) feeding into a resistive divider. The resistive divider (47.5k/2.5k) scales VSS (t) down by 20 times to give the analog current limit threshold: VACL ( t) = VSS( t) - VOS 20 (7) After the initial timing cycle, SS ramps up from 0V to 1.4V (28A * 50k), ramping VACL (t) from -10mV to 60mV. The ACL amplifier will then limit the inrush current to VACL (t)/ RS. The offset voltage, VOS (10mV) ensures CSS is sufficiently discharged and the ACL amplifier is in current limit mode before GATE start-up. There are two modes of SS ramp up. If SEL is set high and the SS pin floats, an internal current source ramps SS from 0V to 1.4V in about 200s. Connecting an external capacitor, CSS, from SS to ground modifies the ramp to approximate an RC response of:
-t VSS( t) VSS 1 - e RSSCSS
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(6)
(8)
4253a-adjf
17
LTC4253A-ADJ
APPLICATIO S I FOR ATIO
When VACL (t) exceeds VSENSE, the ACL amplifier exits current limit mode and releases its pull-down on GATE. VSS (t) = 20 * (VOS + VSENSE) from Equation 7. So when VSS (t) > 20 * VOS = 0.2V (since VSENSE = 0V), GATE starts to ramp up and SS continues to ramp up. When GATE clears the threshold of the external FET and inrush current starts flowing, VACL (t) = (VSS (t)/20 - VOS) will have a positive offset from zero. VSENSE will show an initial jump to clear this offset before going into analog current limit (Figure 4a). If SEL is set low during SS ramp-up, VSS is servoed when it exceeds 20 * VOS = 0.2V and GATE starts its ramp-up. VSS is servoed at a voltage that is just above 20 * VOS to keep the ACL amplifier off and GATE ramping up freely. Once GATE clears the threshold of the external FET, inrush current starts flowing and VSENSE will jump above VACL (t). This will engage the ACL amplifier and mask off VSS servo so V SS continues its RC ramp-up. In this way, the LTC4253A-ADJ enters analog current limit with VACL (t) = (VSS (t)/20 - VOS) ramping up from close to zero. The resultant inrush current profile presents a smooth ramp up from zero (Figure 4b). If there is little inrush current so the LTC4253A-ADJ does not enter current limit, VSS servo will be masked off when DRAIN goes below 2.39V (VDRNL) and latched off when GATE goes within 2.8V of VIN (VGATEH). A minimum CSS of 5nF is required for the stability of the VSS servo loop. SS is discharged low during UVLO, UV, OV, during the initial timing cycle, a latched circuit breaker fault or the RESET pin going high.
GATE 10V
SS 1V
SENSE 50mV
VOUT 50V 1ms/DIV
4253A F04a
(4a) SEL Set High Figure 4. Two Modes of SS Ramp Up
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GATE GATE is pulled low to VEE under any of the following conditions: in UVLO, when RESET pulls high, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or a latched circuit breaker fault. When GATE turns on, a 50A current source charges the MOSFET gate and any associated external capacitance. VIN limits the gate drive to no more than 14.5V. Gate-drain capacitance (CGD) feedthrough at the first abrupt application of power can cause a gate-source voltage sufficient to turn on the MOSFET. A unique circuit pulls GATE low with practically no usable voltage at VIN, and eliminates current spikes at insertion. A large external gate-source capacitor is thus unnecessary for the purpose of compensating CGD. Instead, a smaller value (10nF) capacitor CC is adequate. CC also provides compensation for the analog current limit loop. GATE has two comparators: the GATE low comparator looks for < 0.5V threshold prior to initial timing; the GATE high comparator looks for < 2.8V relative to VIN and, together with DRAIN low comparator, starts power good sequencing during GATE start-up. SENSE The SENSE pin is monitored by the circuit breaker (CB) comparator, the analog current limit (ACL) amplifier, and the fast current limit (FCL) comparator. Each of these three measures the potential of SENSE relative to VEE. When
GATE 10V SS 1V SENSE 50mV VOUT 50V 1ms/DIV
4253A F04b
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(4b) SEL Set Low
4253a-adjf
LTC4253A-ADJ
APPLICATIO S I FOR ATIO
SENSE exceeds 50mV, the CB comparator activates the 200A TIMER pull-up. At 60mV the ACL amplifier servos the MOSFET current, and at 200mV the FCL comparator abruptly pulls GATE low in an attempt to bring the MOSFET current under control. If any of these conditions persists long enough for TIMER to charge CT to 4V (see Equation 4), the LTC4253A-ADJ shuts down and pulls GATE low. If the SENSE pin encounters a voltage greater than VACL, the ACL amplifier will servo GATE downwards in an attempt to control the MOSFET current. Since GATE overdrives the MOSFET in normal operation, the ACL amplifier needs time to discharge GATE to the threshold of the MOSFET. For a mild overload the ACL amplifier can control the MOSFET current, but in the event of a severe overload the current may overshoot. At SENSE = 200mV the FCL comparator takes over, quickly discharging the GATE pin to near VEE potential. FCL then releases, and the ACL amplifier takes over. All the while TIMER is running. The effect of FCL is to add a nonlinear response to the control loop in favor of reducing MOSFET current. Owing to inductive effects in the system, FCL typically overcorrects the current limit loop, and GATE undershoots. A zero in the loop (resistor RC in series with the gate capacitor) helps the ACL amplifier to recover. SHORT-CIRCUIT OPERATION Circuit behavior arising from a load side low impedance short is shown in Figure 5. Initially the current overshoots the analog current limit level of VSENSE = 200mV (trace 2) as the GATE pin works to bring VGS under control (trace 3). The overshoot glitches the backplane in the negative direction and when the current is reduced to 60mV/RS, the backplane responds by glitching in the positive direction. TIMER commences charging CT (trace 4) while the analog current limit loop maintains the fault current at 60mV/RS, which in this case is 5A (trace 2). Note that the backplane voltage (trace 1) sags under load. Timer pull-up is accelerated by VOUT. When CT reaches 4V, GATE turns off, the PWRGD signals pull high, the load current drops to zero and the backplane rings up to over 100V. The transient associated with the GATE turn-off can be controlled with a snubber to reduce ringing and a transient voltage
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suppressor (such as Diodes Inc. SMAT70A), to clip off large spikes. The choice of RC for the snubber is usually done experimentally. The value of the snubber capacitor is usually chosen between 10 to 100 times the MOSFET COSS. The value of the snubber resistor is typically between 3 to 100. A low impedance short on one card may influence the behavior of others sharing the same backplane. The initial glitch and backplane sag as seen in Figure 5 trace 1, can rob charge from output capacitors on the adjacent card. When the faulty card shuts down, current flows in to refresh the capacitors. If LTC4253A-ADJs are used by the other cards, they respond by limiting the inrush current to a value of VACL/RS. If CT is sized correctly, the capacitors will recharge long before CT times out. MOSFET SELECTION The external MOSFET switch must have adequate safe operating area (SOA) to handle short-circuit conditions until TIMER times out. These considerations take precedence over DC current ratings. A MOSFET with adequate SOA for a given application can always handle the required current but the opposite may not be true. Consult the manufacturer's MOSFET datasheet for safe operating area and effective transient thermal impedance curves.
SUPPLY RING OWING TO MOSFET TURN-OFF SUPPLY RING OWING TO CURRENT OVERSHOOT TRACE 1 -48V RTN 50V SENSE 200mV ONSET OF OUTPUT SHORT CIRCUIT TRACE 2 FAST CURRENT LIMIT GATE 10V ANALOG CURRENT LIMIT TIMER 5V LATCH OFF
4253A F05
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TRACE 3 TRACE 4
CTIMER RAMP 0.5ms/DIV
Figure 5. Output Short-Circuit Behavior of LTC4253A-ADJ
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APPLICATIO S I FOR ATIO
MOSFET selection is a 3-step process by assuming the absense of soft-start capacitor. First, RS is calculated and then the time required to charge the load capacitance is determined. This timing, along with the maximum shortcircuit current and maximum input voltage, defines an operating point that is checked against the MOSFET's SOA curve. To begin a design, first specify the required load current and Ioad capacitance, IL and CL. The circuit breaker current trip point (VCB/RS) should be set to accommodate the maximum load current. Note that maximum input current to a DC/DC converter is expected at VSUPPLY(MIN). RS is given by:
RS = VCB(MIN) IL(MAX)
where VCB(MIN) = 45mV represents the guaranteed minimum circuit breaker threshold. During the initial charging process, the LTC4253A-ADJ may operate the MOSFET in current limit, forcing (VACL) between 54mV to 66mV across RS. The minimum inrush current is given by: IINRUSH(MIN) = VACL(MIN) RS (10)
Maximum short-circuit current limit is calculated using the maximum VSENSE. This gives ISHORTCIRCUIT(MAX) = VACL(MAX) RS (11)
The TIMER capacitor, CT, must be selected based on the slowest expected charging rate; otherwise TIMER might time out before the load capacitor is fully charged. A value for CT is calculated based on the maximum time it takes the load capacitor to charge. That time is given by:
tCL(CHARGE) =
C * V C L * VSUPPLY(MAX) = I IINRUSH(MIN)
The maximum current flowing in the DRAIN pin is given by: IDRN(MAX) = VSUPPLY(MAX) - VDRNCL RD (13)
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Approximating a linear charging rate, IDRN drops from IDRN(MAX) to zero, the IDRN component in Equation 4 can be approximated with 0.5 * IDRN(MAX). Rearranging the equation, TIMER capacitor CT is given by:
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CT =
tCL(CHARGE) * (200A + 4 * IDRN(MAX) ) 4V
(14)
Returning to Equation 4, the TIMER period is calculated and used in conjunction with V SUPPLY(MAX) and ISHORTCIRCUIT(MAX) to check the SOA curves of a prospective MOSFET. As a numerical design example, consider a 30W load, which requires 1A input current at 36V. If VSUPPLY(MAX) = 72V and CL = 100F, RD = 1M, Equation 9 gives RS = 45m; use RS = 40m for more margin. Equation 14 gives CT = 619nF. To account for errors in RS, CT, TIMER current (200A), TIMER threshold (4V), RD, DRAIN current multiplier and DRAIN voltage clamp (VDRNCL), the calculated value should be multiplied by 1.5, giving the nearest standard value of CT = 1F. If a short-circuit occurs, a current of up to 66mV/45m = 1.65A will flow in the MOSFET for 9.1ms as dictated by CT = 1F in Equation 4. The MOSFET must be selected based on this criterion. The IRF530S can handle 100V and 2A for 22.5ms and is safe to use in this application. Computing the maximum soft-start capacitor value during soft-start to a load short is complicated by the nonlinear MOSFET's SOA characteristics and the RSSCSS response. An overconservative but simple approach begins with the maximum circuit breaker current, given by: ICB(MAX) = VCB(MAX) RS (15)
(9)
From the SOA curves of a prospective MOSFET, determine the time allowed, tSOA(MAX). CSS is given by: CSS = tSOA(MAX) 2.48 * RSS (16)
(12)
In the above example, 55mV/40m gives 1.375A. tSOA for the IRF530S is 47.6ms. From Equation 16, CSS = 384nF.
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LTC4253A-ADJ
APPLICATIO S I FOR ATIO
Actual board evaluation showed that CSS = 100nF was appropriate. The ratio (RSS * CSS) to tCL(CHARGE) is a good gauge as large ratios may result in the time-out period expiring prematurely. This gauge is determined empirically with board level evaluation. SUMMARY OF DESIGN FLOW To summarize the design flow, consider the application shown in Figure 1. It was designed for 80W and CL = 100F. Calculate maximum load current: 80W/43V = 1.86A; allowing for 83% converter efficiency, IIN(MAX) = 2.2A. Calculate RS: from Equation 9 RS = 20m. Calculate I SHORT-CIRCUIT(MAX) : from Equation 11 ISHORTCIRCUIT(MAX) = 3.3A. Select a MOSFET that can handle 3.3A at 71V: IRF530S. Calculate CT: from Equation 14 CT = 383nF. Select CT = 680nF, which gives the circuit breaker time-out period tMAX = 5.9ms. Consult MOSFET SOA curves: the IRF530S can handle 3.3A at 100V for 8.3ms, so it is safe to use in this application. Calculate CSS: using Equations 15 and 16 select CSS = 33nF. FREQUENCY COMPENSATION The LTC4253A-ADJ typical frequency compensation network for the analog current limit loop is a series RC (10) and CC connected from GATE to VEE. Figure 6 depicts the relationship between the compensation capacitor CC and the MOSFET's CISS. The line in Figure 6 is used to select a starting value for CC based upon the MOSFET's CISS specification. Optimized values for CC are shown for several popular MOSFETs. Differences in the optimized value of CC versus the starting value are small. Nevertheless, compensation values should be verified by board level short-circuit testing. As seen in Figure 5, at the onset of a short-circuit event, the input supply voltage can ring dramatically due to series inductance. If this voltage avalanches the MOSFET, current continues to flow through the MOSFET to the output.
COMPENSATION CAPACITOR CC (nF)
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The analog current limit loop cannot control this current flow and therefore the loop undershoots. This effect cannot be eliminated by frequency compensation. A zener diode is required to clamp the input supply voltage and prevent MOSFET avalanche.
50 45 40 35 30 25 20 15 10 5 0 0 2000 6000 4000 MOSFET CISS (pF) 8000
4253A F06
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NTY100N10
IRF3710 IRF540S IRF740 IRF530S
Figure 6. Recommended Compensation Capacitor CC vs MOSFET CISS
SENSE RESISTOR CONSIDERATIONS For proper circuit breaker operation, Kelvin-sense PCB connections between the sense resistor and the LTC4253AADJ's VEE and SENSE pins are strongly recommended. The drawing in Figure 7 illustrates the correct way of making connections between the LTC4253A-ADJ and the sense resistor. PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation.
CURRENT FLOW FROM LOAD CURRENT FLOW TO -48V BACKPLANE
SENSE RESISTOR TRACK WIDTH W: 0.03" PER AMP ON 1 OZ COPPER W
4253A F07
TO SENSE
TO VEE
Figure 7. Making PCB Connections to the Sense Resistor
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LTC4253A-ADJ
APPLICATIO S I FOR ATIO
TIMING WAVEFORMS System Power-Up
Figure 8 details the timing waveforms for a typical powerup sequence in the case where a board is already installed in the backplane and system power is applied abruptly. At
VIN CLEARS VLKO, CHECK UV > VUVHI, OVL < VOVLO, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 * VOS 12 GND - VEE OR (-48RTN) - (-48V) 3 4 56 7 89 A B C D E
UVL UV OVL OV VIN
VUVHI VOVLO
VLKO VTMRH 5A VTMRL 50A 50A 20 * (VACL + VOS) 20 * (VCB + VOS) 20 * VOS VACL VCB 200A + 8 * IDRN 5A VIN - VGATEH 5A
TIMER
GATE
VGATEL
SS
SENSE VOUT
DRAIN 50A PWRGD1
PWRGD2
PWRGD3 VSQTMRH SQTIMER 5A 5A VSQTMRL VIH
EN2
EN3 GATE START-UP
INITIAL TIMING
Figure 8. System Power-Up Timing (All Waveforms are Referenced to VEE)
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time point 1, the supply ramps up, together with UV/OV, VOUT and DRAIN. VIN and the PWRGD signals follow at a slower rate as set by the VIN bypass capacitor. At time point 2, VIN exceeds VLKO and the internal logic checks for UV > VUVHI, OVL < VOVLO, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS, and TIMER < VTMRL. When
VDRNCL VDRNL VIH
4253A F08
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LTC4253A-ADJ
APPLICATIO S I FOR ATIO
all conditions are met, initial timing starts and the TIMER capacitor is charged by a 5A current source pull-up. At time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < VGATEL, SENSE < VCB and SS < 20 * VOS must be satisfied before the GATE startup cycle begins. SS ramps up as dictated by RSS * CSS (as in Equation 8); GATE is held low by the analog current limit (ACL) amplifier until SS crosses 20 * VOS. Upon releasing GATE, 50A sources into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET's threshold, current flows into the load capacitor at time point 5. At time point 6, load current reaches SS control level and the analog current limit loop activates. Between time points 6 and 8, the GATE voltage is servoed, the SENSE voltage is regulated at VACL(t) (Equation 7) and soft-start limits the slew rate of the load current. If the SENSE voltage (VSENSE - VEE) reaches the VCB threshold at time point 7, circuit breaker TIMER activates. The TIMER capacitor, CT is charged by a (200A + 8 * IDRN) current pull-up. As the load capacitor nears full charge, load current begins to decline. At time point 8, the load current falls and the SENSE voltage drops below VACL(t). The analog current limit loop shuts off and the GATE pin ramps further. At time point 9, the SENSE voltage drops below VCB, the fault TIMER ends, followed by a 5A discharge cycle (cool-off). The duration between time points 7 and 9 must be shorter than one circuit breaker delay to avoid fault time-out during GATE rampup. At time point B, GATE reaches its maximum voltage as determined by VIN. At time point A, GATE ramps past VGATEH and SQTIMER starts its ramp-up to 4V. PWRGD1 pulls low at time point C after one tSQT from time point A, setting off the second SQTIMER ramp up. Having satisfied the requirement that PWRGD1 is low for more than one tSQT, PWRGD2 pulls low after EN2 pulls high above the VIH threshold at time point D. This sets off the third SQTIMER ramp-up. Having satisfied the requirement that PWRGD2 is low for more than one tSQT, PWRGD3 pulls low after EN3 pulls high at time point E.
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Live Insertion with Short Pin Control of UV/OV In the example shown in Figure 9, power is delivered through long connector pins whereas the UV/OV divider makes contact through a short pin. This ensures the power connections are firmly established before the LTC4253A-ADJ is activated. At time point 1, the power pins make contact and VIN ramps through VLKO. At time point 2, the UV/OV divider makes contact and UV > VUVHI. In addition, the internal logic checks for OV < VOVHI, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS and TIMER < VTMRL. When all conditions are met, initial timing starts and the TIMER capacitor is charged by a 5A current source pullup. At time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < V GATEL, SENSE < VCB and SS < 20 * VOS must be satisfied before the GATE start-up cycle begins. SS ramps up as dictated by RSS * CSS; GATE is held low by the analog current limit amplifier until SS crosses 20 * VOS. Upon releasing GATE, 50A sources into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET's threshold, current begins flowing into the load capacitor at time point 5. At time point 6, load current reaches SS control level and the analog current limit loop activates. Between time points 6 and 8, the GATE voltage is servoed and the SENSE voltage is regulated at VACL(t) and soft-start limits the slew rate of the load current. If the SENSE voltage (VSENSE - VEE) reaches the VCB threshold at time point 7, the circuit breaker TIMER activates. The TIMER capacitor, CT is charged by a (200A + 8 * IDRN) current pull-up. As the load capacitor nears full charge, load current begins to decline. At point 8, the load current falls and the SENSE voltage drops below VACL(t). The analog current limit loop shuts off and the GATE pin ramps further. At time point 9, the SENSE voltage drops below VCB and the fault TIMER ends, followed by a 5A discharge current source (cool-off). When GATE ramps past VGATEH threshold at time point A, SQTIMER starts its ramp-up. PWRGD1 pulls low at time point C after one tSQT from time
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LTC4253A-ADJ
APPLICATIO S I FOR ATIO
point A, setting off the second SQTIMER ramp-up. PWRGD2 pulls low at time point D when EN2 is high and PWRGD1 is low for more than one tSQT. PWRGD3 pulls low at time point E when EN2 and EN3 is high and PWRGD2 is low for more than one tSQT. At time point B, GATE reaches its maximum voltage as determined by VIN.
UV CLEARS VUVHI, CHECK OV < VOVHI, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 * VOS 1 GND - VEE OR (-48RTN) - (-48V) 2 3 456 7 89 A B C D E
UVL UV
VUVHI VOVHI
OVL OV VIN VLKO VTMRH TIMER 5A VTMRL 50A GATE VGATEL 20 * (VACL + VOS) 20 * (VCB + VOS) 20 * VOS VACL SENSE VOUT VDRNCL DRAIN 50A PWRGD1 VDRNL VCB 50A 200A + 8 * IDRN 5A 5A
SS
PWRGD2
PWRGD3 VSQTMRH SQTIMER 5A 5A VSQTMRL
EN2
EN3 INITIAL TIMING GATE START-UP
4253A F09
Figure 9. Power-Up Timing with a Short Pin (All Waveforms are Referenced to VEE)
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Undervoltage Timing In Figure 10 when the UVL pin drops below VUVLO (time point 1), the LTC4253A-ADJ shuts down with TIMER, SS and GATE pulled low. If current has been flowing, the SENSE pin voltage decreases to zero as GATE collapses. When UV recovers and clears VUVHI (time point 2), an initial time cycle begins followed by a start-up cycle.
VIN - VGATEH
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LTC4253A-ADJ
APPLICATIO S I FOR ATIO
UVL DROPS BELOW VUVLO. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES UV CLEARS VUVHI, CHECK OV CONDITION, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 * VOS 1 UVL UV VUVLO VUVHI VTMRH TIMER 5A VTMRL 50A GATE VGATEL 20 * (VACL + VOS) 20 * (VCB + VOS) 20 * VOS VACL SENSE VCB VDRNCL DRAIN 50A PWRGD1 VDRNL 50A 200A + 8 * IDRN 5A 5A VIN - VGATEH 2 3 4 56 7 89 A B C D E
SS
PWRGD2
PWRGD3 VSQTMRH SQTIMER 5A 5A VSQTMRL EN2
EN3 GATE START-UP
INITIAL TIMING
Figure 10. Undervoltage Timing (All Waveforms are Referenced to VEE)
VIN Undervoltage Lockout Timing VIN undervoltage lockout comparator, UVLO has a similar timing behavior as the UV pin timing except it looks at VIN < (VLKO - VLKH) to shut down and VIN > VLKO to start. In an undervoltage lockout condition, both UV and OV comparators are held off. When VIN exits undervotlage lockout, the UV and OV comparators are enabled.
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4253 F10
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Overvoltage Timing During normal operation, if the OV pin exceeds VOVHI as shown at time point 1 of Figure 11, the TIMER and PWRGD status are unaffected; SS and GATE pull down; load disconnects. At time point 2, OVL recovers and drops below the VOVLO threshold; GATE start-up begins. If the overvoltage glitch is long enough to deplete the load capacitor, time points 4 through 7 may occur.
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LTC4253A-ADJ
APPLICATIO S I FOR ATIO
1 VOVHI OVL OV VTMRH TIMER 2 34
OV OVERSHOOTS VOVHI. GATE AND SS ARE PULLED DOWN, PWRGD SIGNALS AND TIMER ARE UNAFFECTED OVL DROPS BELOW VOVLO, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 * VOS 5 67 8 9
VOVLO
200A + 8 * IDRN
GATE VGATEL
50A
20 * (VACL + VOS) SS 20 * (VCB + VOS) 20 * VOS VACL SENSE VCB
4253A F11
GATE START-UP
Figure 11. Overvoltage Timing (All Waveforms are Referenced to VEE)
Circuit Breaker Timing In Figure 12a, the TIMER capacitor charges at 200A if the SENSE pin exceeds VCB but VDRN is less than 5V. If the SENSE pin returns below VCB before TIMER reaches the VTMRH threshold, TIMER is discharged by 5A. In Figure 12b, when TIMER exceeds VTMRH, GATE pulls down immediately and the chip shuts down. In Figure 12c, multiple momentary faults cause the TIMER capacitor to integrate and reach VTMRH followed by GATE pull down and the chip shuts down. During chip shutdown, LTC4253A-ADJ latches TIMER high with a 5A pull-up current source. Resetting a Fault Latch A latched circuit breaker fault of the LTC4253A-ADJ has the benefit of a long cooling time. The latched fault can be reset by pulsing the RESET pin high for >20s to overcome the internal glitch filter as shown in Figure 13b. After the RESET pulse, SS and GATE ramp up without an initial timing cycle provided the interlock conditions are satisfied.
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5A 5A 50A VIN - VGATEH
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Alternative methods of reset include using an external switch to pulse the UVL/UV pin below VUVLO or the VIN pin below (VLKO - VLKH). Pulling the TIMER pin below VTMRL and the SS pin to 0V then simultaneously releasing them also achieves a reset. An initial timing cycle is generated for reset by pulsing the UVL/UV pin or VIN pin, while no initial timing cycle is generated for reset by pulsing of the TIMER and SS pins. Using Reset as an ON/OFF Switch The asynchronous RESET pin can be used as an on/off function to cut off supply to the external power modules or loads controlled by the chip. Pulling RESET high will pull GATE, SS, TIMER and SQTIMER low and the PWRGD signal high. The supply is fully cut off if the RESET pulse is maintained wide enough to overcome the internal 20s glitch filter. As long as RESET is high, GATE, SS, TIMER and SQTIMER are strapped to VEE and the supply is cut off. When RESET is released, the chip waits for the interlock conditions before recovering as described in the Operation, Interlock Conditions section and Figure 13c.
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LTC4253A-ADJ
APPLICATIO S I FOR ATIO
1 200A + 8 * IDRN TIMER 2 VTMRH 5A
GATE
SS VACL SENSE VOUT VCB
DRAIN
PWRGD1
CB FAULT
(12a) Momentary Circuit Breaker Fault
Figure 12. Circuit Breaker Timing Behavior (All Waveforms are Referenced to VEE)
Analog Current Limit and Fast Current Limit In Figure 14a, when SENSE exceeds VACL, GATE is regulated by the analog current limit amplifier loop. When SENSE drops below VACL, GATE is allowed to pull up. In Figure 14b, when a severe fault occurs, SENSE exceeds VFCL and GATE immediately pulls down until the analog current amplifier establishes control. If the severe fault causes VOUT to exceed VDRNCL, the DRAIN pin is clamped at VDRNCL. IDRN flows into the DRAIN pin and is multiplied by 8. This extra current is added to the TIMER pull-up current of 200A. This accelerated TIMER current of (200A + 8 * IDRN) produces a shorter circuit breaker fault delay. Careful selection of CT, RD and MOSFET helps prevent SOA damage in a low impedance fault condition. Soft-Start If SEL is floated high and the SS pin is not connected, this pin defaults to a linear voltage ramp, from 0V to 1.4V in about 200s at GATE start-up, as shown in Figure 15a. If a soft-start capacitor, CSS, is connected to this SS pin, the
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CB TIMES-OUT 1 VTMRH 200A + 8 * IDRN TIMER 2 CB TIMES-OUT 1 2 3 VTMRH 200A + 8 * IDRN TIMER 5A 4 GATE GATE SS VACL SENSE VOUT VDRNCL DRAIN DRAIN VCB SENSE VOUT VDRNCL SS VACL VCB PWRGD1 PWRGD1 CB FAULT CB FAULT CB FAULT
4253A F12
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(12b) Circuit Breaker Time-Out
(12c) Multiple Circuit Breaker Fault
soft-start response is modified from a linear ramp to an RC response (Equation 8), as shown in Figure 15b. This feature allows load current to slowly ramp-up at GATE start-up. Soft-start is initiated at time point 3 by a TIMER transition from VTMRH to VTMRL (time points 1 and 2), by the OVL pin falling below the VOVLO threshold after an OV condition, or by the RESET pin falling < 0.8V after a Reset condition. When the SS pin is below 0.2V, the analog current limit amplifier keeps GATE low. Above 0.2V, GATE is released and 50A ramps up the compensation network and GATE capacitance at time point 4. Meanwhile, the SS pin voltage continues to ramp up. When GATE reaches the MOSFET's threshold, the MOSFET begins to conduct. Due to the MOSFET's high gm, the MOSFET current quickly reaches the soft-start control value of VACL(t) (Equation 7). At time point 6, the GATE voltage is controlled by the current limit amplifier. The soft-start control voltage reaches the circuit breaker voltage, VCB at time point 7 and the circuit breaker TIMER activates. As the load capacitor nears full charge, load current begins
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TIMER TIMER TIMER 5A 50A VIN - VGATEH GATE VGATEL 20 * (VACL + VOS) SS 20 * VOS VACL 20s SENSE SENSE VDRNCL DRAIN VDRNL 50A DRAIN 50A VCB VACL VCB VDRNCL VDRNL 20 * (VCB + VOS) 50A 50A 50A VIN - VGATEH VTMRL 5A 20s GATE VGATEL 20 * (VACL + VOS) SS 20 * VOS 20 * (VCB + VOS) VTMRL
200A + 8 * IDRN 5A 5A 5A 200A + 8 * IDRN 200A + 8 * IDRN
VTMRL
5A
LTC4253A-ADJ
GATE
50A
VIN - VGATEH
VGATEL
50A
20 * (VACL + VOS)
SS
20 * (VCB + VOS)
VACL
APPLICATIO S I FOR ATIO
SENSE
VCB
VDRNCL
VDRNL
50A
PWRGD1 tSQT tSQT PWRGD1 PWRGD1
tSQT
VIN VIN VLKO
VLKO
VIN
VLKO
UVL VUVHI
VUVHI
UVL UV
UVL UV
VUVHI
UV RESET VIH VIL RESET PULSE WIDTH MUST BE >20s TO OVERCOME INTERNAL GLITCH FILTER RESET PULSE WIDTH MUST BE >20s TO OVERCOME INTERNAL GLITCH FILTER RESET
RESET
VIH VIL
4253A F13
VIL
(13a) Reset Forcing Start-Up Without Initial TIMER Cycle
(13b) Reset of LTC4253-ADJ's Latched Fault Figure 13. Reset Functions (All Waveforms are Referenced to VEE)
(13c) Reset as an ON/OFF Switch
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DRAIN
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20 * VOS
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LATCHED TIMER RESET BY RESET PULLING HIGH 1 2 34 5 67 8 9 1 2 34 5 67 8 9 VTMRH 5A RESET < VIL, CHECK UVLO, UV, OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS AND TIMER < VTMRL RESET < VIL, CHECK UVLO, UV, OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS AND TIMER < VTMRL
RESET < VIL, CHECK UVLO, UV, OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS AND TIMER < VTMRL
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LTC4253A-ADJ
APPLICATIO S I FOR ATIO
12 VTMRH 200A + 8 * IDRN TIMER GATE 34 5A
SS VACL SENSE VCB SENSE
VOUT
DRAIN
PWRGD1
(14a) Analog Current Limit Fault
Figure 14. Current Limit Behavior (All Waveforms are Referenced to VEE)
END OF INITIAL TIMING CYCLE 12 3 4 5 6 7 VTMRH TIMER VTMRL 50A GATE VGS(th) 50A SS VIN - VGATEH GATE 200A + 8 * IDRN 5A TIMER 7a 89 10 11
END OF INITIAL TIMING CYCLE 12 3 4 56 VTMRH 200A + 8 * IDRN VTMRL 50A VIN - VGATEH VGS(th) 50A 20 * (VACL + VOS) SS GATE 5A TIMER 7 89 10 11
20 * (VACL + VOS) SS 20 * (VCB + VOS) 20 * VOS VACL SENSE VCB VDRNCL DRAIN VDRNL DRAIN SENSE
(15a) Without External CSS
Figure 15. Soft-Start Timing (All Waveforms are Referenced to VEE)
to decline below VACL(t). The current limit loop shuts off and GATE releases at time point 8. At time point 9, SENSE voltage falls below VCB and TIMER deactivates. A third Soft-Start mode is shown in Figure 15c. The SEL pin is tied low and a soft-start capacitor, CSS, is connected to the SS pin. The behavior is similar to Figure 15b until time point 4 when GATE is released and starts to ramp up. Instead of continuing its ramp-up as in mode two, the SS
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CB TIMES-OUT 1 VTMRH 200A + 8 * IDRN TIMER GATE 2 VFCL VACL VCB VOUT VDRNCL DRAIN PWRGD1
4253A F14
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(14b) Fast Current Limit Fault
END OF INITIAL TIMING CYCLE 12 3 4 56 VTMRH VTMRL 200A + 8 * IDRN 5A 50A VIN - VGATEH VGS(th) 50A 20 * (VACL + VOS) 20 * (VCB + VOS) 20 * VOS VACL VCB SENSE VACL VCB VDRNCL DRAIN VDRNL
4253A F15
7
89
10
11
20 * (VCB + VOS) 20 * VOS
VDRNCL VDRNL
(15b) With External CSS
(15c) With SEL = Low and External CSS
pin voltage is servoed at a voltage that is just above 0.2V (20 * VOS) to keep the current limit amplifier off and the GATE ramping up freely. At time point 5, GATE ramps past the external MOSFET's threshold and inrush current starts to flow. At time point 6, VSENSE goes above VACL (t) and the servo on SS is released while the GATE voltage is controlled by the current limit amplifier with VACL (t) ramping up from near zero. The result is a current profile (as
4253a-adjf
29
LTC4253A-ADJ
APPLICATIO S I FOR ATIO
reflected in VSENSE) that ramps up smoothly from near zero. VSENSE does not show a large kink as in Figure 15b when VACL (t) already has a substantial offset from zero at time point 6. SEL tied low chooses this SS servo mode during soft-start while SEL set high allows the SS pin to do an open-loop ramp-up as in Figures 15a and 15b. The stability of the SS servo loop requires a CSS > 5nF. Large values of CSS can cause premature circuit breaker time-out as VACL(t) may marginally exceed the VCB potential during the circuit breaker delay. The load capacitor is unable to achieve full charge in one GATE start-up cycle. A more serious side effect of a large CSS value is that SOA duration may be exceeded during soft-start into a low impedance load. A soft-start voltage below VCB will not activate the circuit breaker TIMER. Power Limit Circuit Breaker Figure 16 shows the LTC4253A-ADJ in a power limit circuit breaking application. The SENSE pin is modulated by board voltage VSUPPLY. The zener voltage, VZ of D1, is set to be the same as the lowest operating voltage, VSUPPLY(MIN) = 43V. If the goal is to have the high supply operating voltage, VSUPPLY(MAX) = 71V give the same power as available at VSUPPLY(MIN), then resistors R4 and
- 48V RTN (LONG PIN) RIN 10k 20k(1/4W)/2 R4 31.6k R9 22k Q2 FZT857
RESET (LONG PIN) - 48V RTN (SHORT PIN) 2k 1% 255k 1% R2 2.05k 1%
CIN 1F D1 BZV85C43 RESET R3 VIN LTC4253A-ADJ
UVL C1 10nF UV OVL CSS 33nF OV SS SQTIMER CSQ 0.1F TIMER SEL CT 0.68F
PWRGD1 PWRGD2 PWRGD3 EN3 EN2 DRAIN GATE SENSE VEE R5 22 RC 10 Q1 IRF530S VIN1 POWER MODULE 1 OUTPUT RD 1M EN3 EN2 VIN1 POWER MODULE 2 OUTPUT
R1 20k 1% - 48V (LONG PIN)
Figure 16. Power Limit Circuit Breaker Application
4253a-adjf
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R5 are selected by:
R5 VCB = R4 VSUPPLY(MAX)
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(17)
If R5 is 22, then R4 is 31.6k. The peak circuit breaker power limit is:
(VSUPPLY(MIN) + VSUPPLY(MAX) )2 POWER(MAX) =
* POWER AT VSUPPLY(MIN)
4 * VSUPPLY(MIN) * VSUPPLY(MAX) (18)
= 1.064 * POWER AT VSUPPLY(MIN)
when VSUPPLY = 0.5 * (VSUPPLY(MIN) + VSUPPLY(MAX)) = 57V The peak power at the fault current limit occurs at the supply overvoltage threshold. The fault current limited power is:
POWER(FAULT) =
( VSUPPLY ) * V
RS
C2 100F VIN1
ACL
- ( VSUPPLY - VZ ) *
R5 R4
(19)
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C3 0.1F POWER MODULE 1 EN
R6 2.2k
R7 2.2k
R8 2.2k
POWER MODULE 2 EN
LOAD 3
EN

CC 10nF
RS 0.02
MOC207
4253A F16
LTC4253A-ADJ
PACKAGE DESCRIPTIO
.254 MIN
.0165 .0015 RECOMMENDED SOLDER PAD LAYOUT
.0075 - .0098 (0.19 - 0.25) .016 - .050 (0.406 - 1.270)
NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS)
3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.70 0.05 4.50 0.05 3.10 0.05 2.45 0.05 (4 SIDES)
0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-1)--TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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GN Package 20-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005
.337 - .344* (8.560 - 8.738) 20 19 18 17 16 15 14 13 12 11
.058 (1.473) REF
.150 - .165
.229 - .244 (5.817 - 6.198)
.150 - .157** (3.810 - 3.988)
.0250 BSC
1
.0532 - .0688 (1.35 - 1.75)
23
4
56
7
8
9 10
.004 - .0098 (0.102 - 0.249)
.015 .004 x 45 (0.38 0.10) 0 - 8 TYP
.008 - .012 (0.203 - 0.305) TYP
.0250 (0.635) BSC
GN20 (SSOP) 0204
UF Package 20-Lead Plastic QFN (4mm x 4mm)
(Reference LTC DWG # 05-08-1710)
BOTTOM VIEW--EXPOSED PAD 4.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 2.45 0.10 (4-SIDES) 0.75 0.05 R = 0.115 TYP 19 20 0.38 0.10 1 2 PIN 1 NOTCH R = 0.30 TYP
PACKAGE OUTLINE 0.200 REF 0.00 - 0.05
(UF20) QFN 10-04
0.25 0.05 0.50 BSC
4253a-adjf
31
LTC4253A-ADJ
APPLICATIO S I FOR ATIO
Circuit Breaker with Foldback Current Limit
Figure 17 shows the LTC4253A-ADJ in a foldback current limit application. When VOUT is shorted to the - 48V RTN supply, current flows through resistors R4 and R5. This results in a voltage drop across R5 and a corresponding reduction in voltage drop across the sense resistor, RS, as the ACL amplifier servos the sense voltage between the
- 48V RTN (LONG PIN) - 48V RTN (SHORT PIN) 2k 1% 255k 1% R2 2.05k 1% RESET (LONG PIN) C1 10nF CSS 33nF R1 20k 1% R11 47k CSQ 0.1F RIN 10k 20k(1/4W)/2
VIN CIN 1F R6 100k R7 100k R8 100k
R3
VIN EN2 EN3 LTC4253A-ADJ UVL UV OVL OV RESET DRAIN SS SQTIMER TIMER VEE CT 1F GATE SENSE SEL PWRGD1 PWRGD2 PWRGD3 RD 3.3M
- 48V (LONG PIN)
Figure 17. -48V/2.5A Application with Foldback Current Limiting and Transistor Enabled Sequencing Without Feedback
RELATED PARTS
PART NUMBER LT1640AH/LT1640AL LT1641-1/LT1641-2 LTC1642 LT4250 LTC4251/LTC4251-1 LTC4251-2 LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2 LTC4260 DESCRIPTION Negative High Voltage Hot Swap Controllers in SO-8 Positive High Voltage Hot Swap Controllers in SO-8 Fault Protected Hot Swap Controller - 48V Hot Swap Controller - 48V Hot Swap Controllers in SOT-23 - 48V Hot Swap Controllers in MS8/MS10 Positive Voltage Hot Swap Controller with I2C Compatible Monitoring COMMENTS Negative High Voltage Supplies from -10V to -80V Supplies from 9V to 80V, Autoretry/Latched Off 3V to 16.5V, Overvoltage Protection up to 33V Active Current Limiting, Supplies from - 20V to - 80V Fast Active Current Limiting, Supplies from - 15V Fast Active Current Limiting, Supplies from - 15V, Drain Accelerated Response, 1% Accurate UV/OV Thresholds Onboard ADC for Current and Voltage Monitoring, 8.5V to 80V Operation
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
www.linear.com
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SENSE and VEE pins to about 60mV. The short-circuit current through RS reduces as the VOUT voltage increases during an output short-circuit condition. Without foldback current limiting resistor R5, the current is limited to 3A during analog current limit. With R5, the short-circuit current is limited to 0.5A when VOUT is shorted to 71V.
+
C2 100F C3 0.1F R9 100k POWER MODULE 1 EN POWER MODULE 2 EN

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POWER MODULE 3 EN
POWER MODULE 4 EN
R10 3k
4253 F17
VOUT R4 38.3k
FMMT493
Q1 IRF530S RC 10 RS 0.02
R5 22 CC 10nF
4253a-adjf LT/TP 0805 500 * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2005

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